There is a general need for materials with low dielectric constants (low-k) in the integrated circuit manufacturing industry. Using low-k materials as the interlayer dielectric (ILD) of conductive interconnects reduces the delay in signal propagation and signal crosstalk due to capacitive effects. The lower the dielectric constant of the dielectric, the lower the capacitance of the dielectric and the RC delay in the lines and signal crosstalk between electrical lines of the integrated circuit (IC). Further, the use of a low-k material as an interlayer dielectric reduces the power consumption of complex integrated circuits.
Low dielectric constant (k) (“low-k”), insulators, with k significantly lower than that of SiO2 (3.9), are now used as inter-layer dielectric, e.g., as inter-metal dielectric (IMD) for reducing capacitive coupling and improving switching performance of integrated circuits (IC). For example, porous carbon doped silicon dioxide provides a dielectric constant of less than about 3.0.
Cu/IMD integration schemes typically involve the incorporation of other materials along with the bulk inter-metal dielectric material, forming a stack. These other materials may include copper diffusion barrier, copper capping layer and etch stop materials needed to prevent copper poisoning of the bulk low-k dielectric, to protect the relatively soft low-k dielectric, and to facilitate the damascene processing used in the device fabrication. These materials have a substantial impact on the effective k of the IMD stack. For example, an etch stop layer having a higher dielectric constant than the insulating IMD material proximate to it increases the overall (effective) k of the IMD stack. Thus, materials used for etch stop, barrier and capping layers must meet the dual challenges of minimizing the effective k of the stack while providing etch selectivity and protection for the IMD layers.
Barrier and etch stop layers should not only possess a low dielectric constant, but should preferably meet a number of integration requirements. These requirements relate to stability of these layers, their mechanical strength, their stress characteristics and their electrical performance. To meet integration requirements, the chemical, mechanical and electrical characteristics of the barrier and etch stop layers must stay within a certain range. These properties should remain stable while the layers are exposed to ambient conditions after deposition, during subsequent processing, and also during working conditions as part of an IC device. For mechanical strength, integration requires these layers to have high modulus and hardness values, which is correlated to etch selectivity. Films having compressive stress are preferred, because these films can provide mechanical integrity of the interconnect films stack. Lastly, good electrical performance is also required, with leakage currents and breakdown voltage parameters comparable to those of nearby dielectric layers.
There is currently a need for methods to form diffusion barrier layers that would maintain integration requirements relating to stability, mechanical strength and line-to-line leakage. Improved materials and processing are required.